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| ON Semiconductort Zero Voltage Switch Power Controller The UAA2016 is designed to drive triacs with the Zero Voltage technique which allows RFI-free power regulation of resistive loads. Operating directly on the AC power line, its main application is the precision regulation of electrical heating systems such as panel heaters or irons. A built-in digital sawtooth waveform permits proportional temperature regulation action over a 1C band around the set point. For energy savings there is a programmable temperature reduction function, and for security a sensor failsafe inhibits output pulses when the sensor connection is broken. Preset temperature (i.e. defrost) application is also possible. In applications where high hysteresis is needed, its value can be adjusted up to 5C around the set point. All these features are implemented with a very low external component count. * Zero Voltage Switch for Triacs, up to 2.0 kW (MAC212A8) * Direct AC Line Operation * Proportional Regulation of Temperature over a 1C Band * Programmable Temperature Reduction * Preset Temperature (i.e. Defrost) * Sensor Failsafe * Adjustable Hysteresis * Low External Component Count UAA2016 ZERO VOLTAGE SWITCH POWER CONTROLLER SEMICONDUCTOR TECHNICAL DATA 8 1 P SUFFIX PLASTIC PACKAGE CASE 626 8 1 D SUFFIX PLASTIC PACKAGE CASE 751 (SO-8) PIN CONNECTIONS Vref 1 Hys. Adj. 2 Failsafe Sense Input 3 + Sampling Full Wave Logic 1/2 Internal Reference 8 7 6 5 (Top View) Sync VCC Output VEE UAA2016 Pulse Amplifier 6 Output Sensor 3 Temp. Reduc. 4 Temperature Reduction 4 + + + 7 +VCC ORDERING INFORMATION Device UAA2016D Operating Temperature Range TA = - 20 to +85C Package SO-8 Plastic DIP Hysteresis Adjust Voltage Reference 2 4-Bit DAC Synchronization Supply Voltage UAA2016P 1 11-Bit Counter 8 Sync 5 VEE Representative Block Diagram (c) Semiconductor Components Industries, LLC, 2001 1 August, 2001 - Rev. 7 Publication Order Number: UAA2016/D UAA2016 MAXIMUM RATINGS (Voltages referenced to Pin 7) Rating Supply Current (IPin 5) Non-Repetitive Supply Current (Pulse Width = 1.0 s) AC Synchronization Current Pin Voltages Symbol ICC ICCP Isync VPin 2 VPin 3 VPin 4 VPin 6 IPin 1 IO PD RJA TA Value 15 200 3.0 0; Vref 0; Vref 0; Vref 0; VEE 1.0 150 625 100 - 20 to + 85 Unit mA mA mA V Vref Current Sink Output Current (Pin 6) (Pulse Width < 400 s) Power Dissipation Thermal Resistance, Junction-to-Air Operating Temperature Range mA mA mW C/W C ELECTRICAL CHARACTERISTICS (TA = 25C, VEE = -7.0 V, voltages referred to Pin 7, unless otherwise noted.) Characteristic Supply Current (Pins 6, 8 not connected) (TA = - 20 to + 85C) Stabilized Supply Voltage (Pin 5) Reference Voltage (Pin 1) Output Pulse Current (TA = - 20 to + 85C) (Rout = 60 W, VEE = - 8.0 V) Output Leakage Current (Vout = 0 V) Output Pulse Width (TA = - 20 to + 85C) (Note 1) (Mains = 220 Vrms, Rsync = 220 k) Comparator Offset (Note 5) Sensor Input Bias Current Sawtooth Period (Note 2) Sawtooth Amplitude (Note 6) Temperature Reduction Voltage (Note 3) (Pin 4 Connected to VCC) Internal Hysteresis Voltage (Pin 2 Not Connected) Additional Hysteresis (Note 4) (Pin 2 Connected to VCC) Failsafe Threshold (TA = - 20 to + 85C) (Note 7) (ICC = 2.0 mA) Symbol ICC -- VEE Vref IO 90 IOL TP 50 Voff IIB TS AS VTR 280 VIH -- VH 280 VFSth 180 350 -- 420 300 mV 10 -- mV 350 420 mV -10 -- -- 50 -- -- -- 40.96 70 100 +10 0.1 -- 90 mV A sec mV mV -- 100 -- 130 10 A s -10 - 6.5 0.9 - 9.0 - 5.5 1.5 - 8.0 - 4.5 V V mA Min Typ Max Unit mA NOTES: 1. Output pulses are centered with respect to zero crossing point. Pulse width is adjusted by the value of Rsync. Refer to application curves. 2. The actual sawtooth period depends on the AC power line frequency. It is exactly 2048 times the corresponding period. For the 50 Hz case it is 40.96 sec. For the 60 Hz case it is 34.13 sec. This is to comply with the European standard, namely that 2.0 kW loads cannot be connected or removed from the line more than once every 30 sec. 3. 350 mV corresponds to 5C temperature reduction. This is tested at probe using internal test pad. Smaller temperature reduction can be obtained by adding an external resistor between Pin 4 and VCC. Refer to application curves. 4. 350 mV corresponds to a hysteresis of 5C. This is tested at probe using internal test pad. Smaller additional hysteresis can be obtained by adding an external resistor between Pin 2 and VCC. Refer to application curves. 5. Parameter guaranteed but not tested. Worst case 10 mV corresponds to 0.15C shift on set point. 6. Measured at probe by internal test pad. 70 mV corresponds to 1C. Note that the proportional band is independent of the NTC value. 7. At very low temperature the NTC resistor increases quickly. This can cause the sensor input voltage to reach the failsafe threshold, thus inhibiting output pulses; refer to application schematics. The corresponding temperature is the limit at which the circuit works in the typical application. By setting this threshold at 0.05 Vref, the NTC value can increase up to 20 times its nominal value, thus the application works below - 20C. http://onsemi.com 2 UAA2016 S2 RS S1 Rdef R2 R1 R3 3 Sense Input 4 Failsafe + Sampling Full Wave Logic Internal Reference UAA2016 Pulse Amplifier 6 Rout Output +VCC CF 220 Vac Load 7 MAC212A8 NTC Temp. Red. + + + 1/2 4-Bit DAC 2 HysAdj 1 Vref 11-Bit Counter Synchronization Supply Voltage Sync Rsync 8 VEE RS 5 Figure 1. Application Schematic APPLICATION INFORMATION (For simplicity, the LED in series with Rout is omitted in the following calculations.) Triac Choice and Rout Determination The load current is then: I Load + (Vrms 2 sin(2pft)-V )R TM L Depending on the power in the load, choose the triac that has the lowest peak gate trigger current. This will limit the output current of the UAA2016 and thus its power consumption. Use Figure 4 to determine Rout according to the triac maximum gate current (IGT) and the application low temperature limit. For a 2.0 kW load at 220 Vrms, a good triac choice is the ON Semiconductor MAC212A8. Its maximum peak gate trigger current at 25C is 50 mA. For an application to work down to - 20C, Rout should be 60 . It is assumed that: IGT(T) = IGT(25C) exp (-T/125) with T in C, which applies to the MAC212A8. Output Pulse Width, Rsync where VTM is the maximum on state voltage of the triac, f is the line frequency. Set ILoad = ILatch for t = TP/2 to calculate TP. Figures 6 and 7 give the value of TP which corresponds to the higher of the values of IHold and ILatch, assuming that VTM = 1.6 V. Figure 8 gives the Rsync that produces the corresponding TP. RSupply and Filter Capacitor The pulse with TP is determined by the triac's IHold, ILatch together with the load value and working conditions (frequency and voltage): Given the RMS AC voltage and the load power, the load value is: RL = V2rms/POWER With the output current and the pulse width determined as above, use Figures 9 and 10 to determine RSupply, assuming that the sinking current at Vref pin (including NTC bridge current) is less than 0.5 mA. Then use Figure 11 and 12 to determine the filter capacitor (CF) according to the ripple desired on supply voltage. The maximum ripple allowed is 1.0 V. Temperature Reduction Determined by R1 (Refer to Figures 13 and 14.) http://onsemi.com 3 UAA2016 Proportional Band Room Temperature T (C) Overshoot Time (minutes, Typ.) Time (minutes, Typ.) Heating Power P(W) Time (minutes, Typ.) Proportional Temperature Control D Reduced Overshoot D Good Stability Time (minutes, Typ.) ON/OFF Temperature Control D Large Overshoot D Marginal Stability Figure 2. Comparison Between Proportional Control and ON/OFF Control TP AC Line Waveform IHold TP is centered on the zero-crossing. ILatch Gate Current Pulse T+ P 14 x Rsync ) 7 Vrms 2 x pf 10 5 (s) f = AC Line Frequency (Hz) Vrms = AC Line RMS Voltage (V) Rsync = Synchronization Resistor () Figure 3. Zero Voltage Technique http://onsemi.com 4 UAA2016 CIRCUIT FUNCTIONAL DESCRIPTION Power Supply (Pin 5 and Pin 7) The application uses a current source supplied by a single high voltage rectifier in series with a power dropping resistor. An integrated shunt regulator delivers a VEE voltage of - 8.6 V with respect to Pin 7. The current used by the total regulating system can be shared in four functional blocks: IC supply, sensing bridge, triac gate firing pulses and zener current. The integrated zener, as in any shunt regulator, absorbs the excess supply current. The 50 Hz pulsed supply current is smoothed by the large value capacitor connected between Pins 5 and 7. Temperature Sensing (Pin 3) hysteresis is obtained by connecting Pin 2 to VCC. In that case the level is set at 5C. This configuration can be useful for low temperature inertia systems. Sawtooth Generator In order to comply with European norms, the ON/OFF period on the load must exceed 30 seconds. This is achieved by an internal digital sawtooth which performs the proportional regulation without any additional component. The sawtooth signal is added to the reference applied to the comparator negative input. Figure 2 shows the regulation improvement using the proportional band action. Noise Immunity The actual temperature is sensed by a negative temperature coefficient element connected in a resistor divider fashion. This two element network is connected between the ground terminal Pin 5 and the reference voltage - 5.5 V available on Pin 1. The resulting voltage, a function of the measured temperature, is applied to Pin 3 and internally compared to a control voltage whose value depends on several elements: Sawtooth, Temperature Reduction and Hysteresis Adjust. (Refer to Application Information.) Temperature Reduction The noisy environment requires good immunity. Both the voltage reference and the comparator hysteresis minimize the noise effect on the comparator input. In addition the effective triac triggering is enabled every 1/3 sec. Failsafe Output pulses are inhibited by the "failsafe" circuit if the comparator input voltage exceeds the specified threshold voltage. This would occur if the temperature sensor circuit is open. Sampling Full Wave Logic For energy saving, a remotely programmable temperature reduction is available on Pin 4. The choice of resistor R1 connected between Pin 4 and VCC sets the temperature reduction level. Comparator Two consecutive zero-crossing trigger pulses are generated at every positive mains half-cycle. This ensures that the number of delivered pulses is even in every case. The pulse length is selectable by Rsync connected on Pin 8. The pulse is centered on the zero-crossing mains waveform. Pulse Amplifier When the positive input (Pin 3) receives a voltage greater than the internal reference value, the comparator allows the triggering logic to deliver pulses to the triac gate. To improve the noise immunity, the comparator has an adjustable hysteresis. The external resistor R3 connected to Pin 2 sets the hysteresis level. Setting Pin 2 open makes a 10 mV hysteresis level, corresponding to 0.15C. Maximum 200 R out , OUTPUT RESISTOR ( ) 180 160 140 120 100 80 60 40 20 TA = - 20C TA = -10C 30 40 50 IGT, TRIAC GATE CURRENT SPECIFIED AT 25C (mA) 60 TA = +10C TA = 0C The pulse amplifier circuit sinks current pulses from Pin 6 to VEE. The minimum amplitude is 70 mA. The triac is then triggered in quadrants II and III. The effective output current amplitude is given by the external resistor Rout. Eventually, an LED can be inserted in series with the Triac gate (see Figure 1). I Out(min) , MINIMUM OUTPUT CURRENT (mA) 100 80 60 40 20 0 TA = - 20C TA = + 85C 40 60 80 100 120 140 160 Rout, OUTPUT RESISTOR () 180 200 Figure 4. Output Resistor versus Triac Gate Current Figure 5. Minimum Output Current versus Output Resistor http://onsemi.com 5 UAA2016 120 TP, OUTPUT PULSE WIDTH ( s) 100 80 60 220 Vrms 40 20 F = 50 Hz 2.0 kW Loads VTM = 1.6 V TA = 25C 110 Vrms 120 TP, OUTPUT PULSE WIDTH ( s) 100 80 60 220 Vrms 40 20 F = 50 Hz 1.0 kW Loads VTM = 1.6 V TA = 25C 60 110 Vrms 0 20 30 40 50 ILatch(max), MAXIMUM TRIAC LATCH CURRENT (mA) 10 60 0 10 20 30 40 50 ILatch(max), MAXIMUM TRIAC LATCH CURRENT (mA) Figure 6. Output Pulse Width versus Maximum Triac Latch Current R sync , SYNCHRONIZATION RESISTOR (k ) 400 R Supply , MAXIMUM SUPPLY RESISTOR (k ) 60 Figure 7. Output Pulse Width versus Maximum Triac Latch Current F = 50 Hz V = 220 Vrms F = 50 Hz 50 TP = 50 s 100 s 30 150 s 200 s 0 25 50 75 IO, OUTPUT CURRENT (mA) 100 300 220 Vrms 200 110 Vrms 40 100 0 20 40 60 80 TP, OUTPUT PULSE WIDTH (s) 100 20 Figure 8. Synchronization Resistor versus Output Pulse Width R Supply, MAXIMUM SUPPLY RESISTOR (k ) 30 C F(min), MINIMUM FILTER CAPACITOR ( F) 90 80 70 60 50 Figure 9. Maximum Supply Resistor versus Output Current V = 110 Vrms F = 50 Hz Ripple = 1.0 Vp-p F = 50 Hz 200 s 150 s 100 s TP = 50 s 25 TP = 50 s 100 s 15 150 s 200 s 0 25 50 75 IO, OUTPUT CURRENT (mA) 100 20 10 40 0 20 40 60 IO, OUTPUT CURRENT (mA) 80 100 Figure 10. Maximum Supply Resistor versus Output Current Figure 11. Minimum Filter Capacitor versus Output Current http://onsemi.com 6 UAA2016 C F(min) , MINIMUM FILTER CAPACITOR ( F) TR , TEMPERATURE REDUCTION ( C) 180 160 140 120 100 80 Ripple = 0.5 Vp-p F = 50 Hz 200 s 150 s 100 s TP = 50 s 0 20 40 60 IO, OUTPUT CURRENT (mA) 80 100 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 10 10 k NTC 100 k NTC 20 30 40 50 60 70 80 90 R1, TEMPERATURE REDUCTION RESISTOR (k) 100 Setpoint = 20C Figure 12. Minimum Filter Capacitor versus Output Current 6.0 5.6 5.2 4.8 4.4 4.0 10 10 k NTC 4 RDEF /(NOMINAL NTC VALUE) RATIO Figure 13. Temperature Reduction versus R1 TR , TEMPERATURE REDUCTION ( C) R1 = 0 100 k NTC 3 10 k NTC 2 100 k NTC 1 14 18 22 26 TS, TEMPERATURE SETPOINT (C) 30 0 0 5 10 15 20 25 TDEF, PRESET TEMPERATURE (C) 30 Figure 14. Temperature Reduction versus Temperature Setpoint 8 V H , COMPARATOR HYSTERESIS VOLTAGE (V) 0.5 0.4 0.3 0.2 0.1 0 Figure 15. RDEF versus Preset Temperature ( R S + R 2 /(NOMINAL NTC VALUE) RATIO TDEF = 4C 6 4 10 k NTC RDEF = 29 k 100 k NTC RDEF = 310 k 14 18 22 26 30 TS, TEMPERATURE SETPOINT (C) 34 2 0 10 0 100 200 300 R3, HYSTERESIS ADJUST RESISTOR (k) 400 Figure 16. RS + R2 versus Preset Setpoint Figure 17. Comparator Hysteresis versus R3 http://onsemi.com 7 UAA2016 PACKAGE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE L NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 8 5 -B- 1 4 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M TA M H G 0.13 (0.005) B M DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040 -X- A 8 5 D SUFFIX PLASTIC PACKAGE CASE 751-07 ISSUE W B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M J ZY S X S ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 UAA2016/D |
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